The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly to measures for attaining a proper impurity concentration distribution in a heterobipolar transistor or a Bi-CMOS device including a heterobipolar transistor.
In recent years, a heterobipolar transistor (HBT) has been developed at rapid paces, which is a bipolar transistor formed on a silicon substrate constructed to include a heterojunction structure such as Si/SiGe and Si/SiC to provide superior conduction property and thus enable operation in a higher frequency range. This type of HBT uses a Si/SiGe heterojunction structure formed by epitaxially growing a SiGe layer on a Si substrate. By use of this structure, it becomes possible to attain transistors operating in a high frequency range in which only transistors using a compound semiconductor substrate such as a GaAs substrate can operate so far. Since this HBT includes a Si substrate and a SiGe layer that are made of materials good in compatibility with the general silicon process, it has great advantages of high integrity and low cost. In particular, by forming a HBT and a MOS transistor (MOSFET) on a common Si substrate for integration, a high-performance Bi-CMOS device can be constructed. Such a Bi-CMOS device is promising as a system LSI usable in the communications industry.
As a bipolar transistor constituting the Bi-CMOS device, HBTs including a heterojunction structure such as Si/Si1-xGex and Si/Si1-yCy have been proposed/prototyped so far. A Si/Si1-xGex HBT, among others, is considered promising from its features including that the band gap can be continuously adjusted using the nature of Si and Ge being solid-soluble to each other in substantially any percentages and the change in band gap with application of strain. For this reason, there have been made a number of proposals on SiGe Bi-CMOS devices in which a MOSFET having only Si layers and a Si/Si1-xGex type HBT are formed on a common Si substrate.
FIG. 12 is a cross-sectional view illustrating a fabrication process of a conventional SiGe Bi-CMOS device. As shown in FIG. 12, the upper portion of a Si substrate 500 using the (001) face as the principal plane is occupied by a retrograde well 501 having a depth of 1 xcexcm containing an n-type impurity such as phosphorus introduced by epitaxial growth, ion implantation, or the like. The concentration of the n-type impurity in a region near the surface of the Si substrate 500 is set to be about 1xc3x971017 atoms.cmxe2x88x923. As device isolation, provided are a shallow trench 503 with silicon oxide buried therein and a deep trench 504 constructed of an undoped polysilicon film 505 and a silicon oxide film 506 surrounding the undoped polysilicon film 505. The depths of the trenches 503 and 504 are about 0.35 xcexcm and about 2 xcexcm, respectively.
A collector layer 502 is provided in the region of the Si substrate 500 sandwiched by the adjacent trenches 503. An n+ collector lead layer 507 for contacting with an electrode of the collector layer 502 via the retrograde well 501 is formed in a region of the Si substrate 500 separated from the collector layer 502 by the shallow trench 503.
A first buried oxide film 508 having a thickness of about 30 nm, which has a collector opening 510, is formed on the Si substrate 500. A Si1-xGex layer 511b, composed of an undoped layer (i-Si1-xGex layer) having a thickness of about 20 nm and a p-type impurity doped layer (p+ Si1-xGex layer) having a thickness of about 40 nm, is formed over the exposed portion of the Si substrate 500 in the collector opening 510 and the first buried oxide film 508. A Si cap layer 511a having a thickness of about 40 nm is then formed on the layer 511b. The Si cap layer 511a and the Si1-xGex layer 511b constitute a Si/Si1-xGex layer 511. The portion of the Si/Si1-xGex layer 511 located in the collector opening 510 has a single-crystal structure formed by epitaxial growth on the underlying Si substrate 500, while the portion thereof located on the buried oxide film 508 has a polycrystal structure.
A second buried oxide film 512 having a thickness of about 30 nm is formed on the Si/Si1-xGex layer 511 to serve as an etch stopper. The second buried oxide film 512 has base junction openings 514 and a base opening 518. A p+ polysilicon layer 515 having a thickness of about 150 nm is formed burying the base junction openings 514 and expanding over the second buried oxide film 512, and a third buried oxide film 517 is formed on the p+ polysilicon layer 515.
An opening is formed through the portion of the p+ polysilicon layer 515 and the portion of the third buried oxide film 517 located above the base opening 518 of the second buried oxide film 512. A fourth buried oxide film 520 having a thickness of about 30 nm is formed on each side face of the p+ polysilicon layer 515, and a sidewall 521 made of polysilicon having a thickness of about 100 nm is formed on the fourth buried oxide film 520. An n+ polysilicon layer 529 is formed burying the base opening 518 and expanding over the third buried oxide film 517. The n+ polysilicon layer 529 functions as an emitter lead electrode. The fourth buried oxide film 520 electrically isolates the p+ polysilicon layer 515 from the n+ polysilicon layer 529, and also blocks diffusion of an impurity from the p+ polysilicon layer 515 into the n+ polysilicon layer 529. Likewise, the third buried oxide film 517 isolates the top surface of the p+ polysilicon layer 515 from the n+ polysilicon layer 529.
Ti silicide layers 524 are formed on the collector lead layer 507, the p+ polysilicon layer 515, and the n+ polysilicon layer 529, and sidewalls 523 cover the outer side faces of the n+ polysilicon layer 529 and the p+ polysilicon layer 515. The entire substrate is covered with an interlayer insulating film 525. Connection holes are formed through the interlayer insulating film 525 to reach the Ti silicide layers 524 on the n+ collector lead layer 507, the p+ polysilicon layer 515 as part of an external base, and the n+ polysilicon layer 529 as the emitter lead electrode. W plugs 526 bury the connection holes, and metal interconnections 527 connected to the W plugs 526 extend on the interlayer insulating film 525.
The structure of the emitter-base junction shown in the partial enlarged view in FIG. 12 will be described. The region of the Si1-xGex layer 511b located under the base opening 518 functions as an internal base (intrinsic base) 519. The region of the Si cap layer 511a located immediately under the base opening 518, which contains boron introduced by diffusion from the n+ polysilicon layer 529, functions as an emitter 530.
The remaining portion of the Si/Si1-xGex layer 511 other than the region under the base opening 518 and the p+ polysilicon layer 515 constitute an external base 516. Note that in the partial enlarged view, the portion of the Si/Si1-xGex layer 511 excluding the region under the base opening 518 functions as the external base 516.
By the construction described above, provided is the Si/SiGe NPN heterobipolar transistor including the n+-type emitter 530 made of Si single crystal, the p+-type internal base 519 mainly made of Si1-xGex single crystal, and the collector layer 502 made of Si single crystal. Note however that the emitter/base/collector are partitioned from one another, not by the boundaries of Si/SiGe crystals, but by changes of the conductivity type of impurities. Therefore, to be precise, the boundaries of the emitter/base/collector vary depending on the profiles of the impurities. In particular, for application as a device for high-frequency signal amplification, the profile of boron (B) as the p-type impurity in the internal base 519 plays a significantly important role. In view of this, the deposition of the Si1-xGex layer 511b is performed in the following manner.
As shown in FIG. 13, after the undoped i-Si1-xGex layer (x is constant) is epitaxially grown on the collector layer (Si substrate), the boron-doped p+ Si1-xGex layer (x varies) and the Si cap layer are epitaxially grown sequentially on the undoped i-Si1-xGex layer. The right side of FIG. 13 shows the distributions of the B concentration and the Ge content during the crystal growth for formation of the base layer. This indicates that the top portion of the p+ Si1-xGex layer, in which the Ge content is substantially zero, is hardly distinguished from the Si cap layer in composition. In a subsequent process including high-temperature treatment, boron in the p+ Si1-xGex layer is diffused, resulting in a slow B concentration distribution with boron spreading into part of the Si cap layer and part of the i-Si1-xGex layer.
Problems to be Solved
In the conventional Si/SiGe heterobipolar transistor, it is difficult to suppress the spread of boron (B) in the Si1-xGex layer 511b during the fabrication process and eventually maintain a proper B concentration profile stably. It has been found that this spread of boron (B) deteriorates the characteristics of the heterobipolar transistor in the high-frequency range. To clarify why the B concentration profile loose stability, the present inventors performed the following experiment.
FIG. 14 is a view showing SIMS measurement data on the concentration distributions of phosphorus (P) and boron (B) and the Ge content in the emitter-base region of the conventional Si/SiGe heterobipolar transistor. Referring to FIG. 14, the x-axis represents the relative depth from point 0 conveniently determined, and the y-axis represents the secondary ion intensity (count number) that corresponds to the concentration (atoms.cmxe2x88x923) of phosphorus (P) or boron (B) and the Ge content. As shown in FIG. 14, the Ge content exhibits a sharp tilt profile indicating that a good composition was obtained. On the contrary, the boron (B) concentration distribution in the p+ Si1-xGex layer is slow, widely spreading into most part of the Si cap layer 511a. Boron (B) has two types, 10B and 11B, different in weight. It is known that, while both 10B and 11B exist in the Si1-xGex layer when boron (B) was introduced into the Si1-xGex layer by in-situ doping during the epitaxial growth, only 11B exists in the Si1-xGex layer when boron (B) was introduced into the Si1-xGex layer by ion implantation. Note that, in the SIMS measurement, since the region of a sample in which atoms such as impurity atoms are sputtered varies to some extent, the SIMS measurement data does not necessarily represent correct correspondence between the range of each region and the impurity concentration. However, the data at least represents a rough tendency between the range of each region and the impurity concentration.
Why the boron (B) concentration distribution spreads wider than expected as shown in FIG. 14 has not yet been clarified completely. However, from the data shown in FIG. 14 and facts revealed from other experiments, it has been found that some correlation exists between the phosphorus concentration and the boron (B) concentration with high possibility. More specifically, a tendency has been recognized that as the phosphorus (P) concentration in the emitter is higher, the boron (B) concentration distribution spreads wider in the p+ Si1-xGex layer. It is considered that point defects are related to this phenomenon, that is, as the phosphorus (P) concentration is higher, diffusion of boron (B) is facilitated. In other words, if point defects exist in a high concentration, B atoms are allowed to diffuse by migration via the point defects, not only by substitution for Si and Ge atoms. This increases the diffusion rate of B atoms during high-temperature treatment, and as a result, the boron (B) concentration distribution becomes slow.
The above phenomenon is induced from the concentration distribution of phosphorus (P) as follows. In the phosphorus (P) concentration distribution in the Si cap layer shown in FIG. 14, a region Re1 contains phosphorus (P) in a concentration exceeding the solid-solubility limit for Si single crystal (about 1xc3x971020 atoms.cmxe2x88x923). The excess amount of the phosphorus (P) exceeding the solid-solubility limit presumably enters inter-lattice spaces or forms voids, thereby generating point defects. In other words, when the phosphorus (P) concentration is high in the Si1-xGex layer, the number of point defects increases, which facilitates diffusion of boron (B) and thus spreads the B concentration distribution.
The n+ polysilicon layer 529 functioning as the conventional emitter lead electrode is doped with phosphorus (P) in a concentration of about 5.0xc3x971020 atoms.cmxe2x88x923 as shown in FIG. 14, which is considerably high compared with the solid-solubility limit for Si single crystal. The reason for this high concentration is as follows. An impurity tends to segregate at grain boundaries in polysilicon. Therefore, if the polysilicon is not doped with phosphorus (P) in a high concentration as a whole, it fails to secure an impurity activation rate required to ensure low resistance.
An object of the present invention is providing a semiconductor device functioning as a bipolar transistor excellent in electric characteristics such as high-frequency characteristics and a method for fabricating such a semiconductor device, in which the concentration distribution of a p-type impurity such as boron (B) in a base layer of the heterobipolar transistor is properly maintained by providing a means for suppressing spread of the p-type impurity into a Si cap layer while keeping the impurity concentration required for securing the low-resistance characteristic of an emitter lead electrode and an emitter and desired operation of the bipolar transistor.
The first semiconductor device of the present invention includes: a substrate including an n-type first single-crystal semiconductor layer functioning as a collector layer; a p-type second single-crystal semiconductor layer formed on the first single-crystal semiconductor layer, functioning as a base layer; a third single-crystal semiconductor layer formed on the second single-crystal semiconductor layer, an upper portion of the third single-crystal semiconductor layer containing phosphorus in a concentration equal to or less than the solid-solubility limit, at least part of the third single-crystal semiconductor layer functioning as an emitter; and an emitter lead electrode formed on the third single-crystal semiconductor layer, the emitter lead electrode being made of a semiconductor layer containing phosphorus in a concentration higher than that in the upper portion of the third single-crystal semiconductor layer.
Thus, since the third single-crystal semiconductor layer functioning as the emitter layer contains phosphorus only in a concentration equal to or lower than the solid-solubility limit, generation of point defects in the third single-crystal semiconductor layer is suppressed. This suppresses diffusion of a p-type impurity, for example, boron, in the second single-crystal semiconductor layer located under the third single-crystal semiconductor layer, and as a result, the p-type impurity concentration distribution is properly maintained in the second single-crystal semiconductor layer.
The second semiconductor device of the present invention includes: a substrate including an n-type first single-crystal semiconductor layer functioning as a collector layer; a p-type second single-crystal semiconductor layer formed on the first single-crystal semiconductor layer, the second single-crystal semiconductor layer containing a p-type impurity and functioning as a base layer; and a third single-crystal semiconductor layer formed on the second single-crystal semiconductor layer, at least an upper portion of the third single-crystal semiconductor layer containing a p-type impurity and phosphorus in a concentration higher than the concentration of the p-type impurity, at least part of the third single-crystal semiconductor layer functioning as an emitter.
It has been found experimentally that if the third single-crystal semiconductor layer contains a p-type impurity, diffusion of a p-type impurity, for example, boron, in the second single crystal layer is suppressed. Therefore, with the above construction, the p-type impurity concentration distribution is properly maintained in the second single-crystal semiconductor layer functioning as the base layer. The upper portion of the third single-crystal semiconductor layer, which functions as the n-type emitter, contains phosphorus in a concentration higher than the concentration of the p-type impurity in this portion. Thus, the function as the bipolar transistor is maintained.
The concentration of the p-type impurity in the upper portion of the third single-crystal semiconductor layer may be equal to or higher than the concentration of the p-type impurity in the second single-crystal semiconductor layer. This further ensures suppression of diffusion of the p-type impurity in the second single-crystal semiconductor layer.
The first single-crystal semiconductor layer may be a Si layer, the second single-crystal semiconductor layer may be a SiGe or SiGeC layer, and the third single-crystal semiconductor layer may be a Si layer. This enables attainment of a Si/SiGe or Si/SiGeC heterobipolar transistor excellent in electric characteristics such as high-frequency characteristics.
The first method for fabricating a semiconductor device of the present invention includes the steps of: (a) epitaxially growing a p-type second single-crystal semiconductor layer functioning as a base layer on an n-type first single-crystal semiconductor layer functioning as a collector layer on a substrate; (b) epitaxially growing a third single-crystal semiconductor layer on the second single-crystal semiconductor layer; (c) depositing a semiconductor layer on the third single-crystal semiconductor layer, the semiconductor layer including a bottom portion containing phosphorus in a concentration equal to or lower than a concentration permitting phosphorus to be diffused into the third single-crystal semiconductor layer in a concentration as high as the solid-solubility limit for the third single-crystal semiconductor layer, and an upper portion containing phosphorus in a concentration higher than that in the bottom portion; and (d) performing heat treatment for diffusing phosphorus in the semiconductor layer so that the upper portion of the third single-crystal semiconductor layer is doped with phosphorus in a concentration equal to or lower than the solid-solubility limit, to form an emitter of a bipolar transistor.
By the above method, during the heat treatment in the step (d), phosphorus is suppressed from diffusing into the third single-crystal semiconductor layer in a concentration exceeding the solid-solubility limit from the bottom portion of the semiconductor layer such as an amorphous silicon layer or a polysilicon layer. This suppresses generation of point defects in the third single-crystal semiconductor layer, and thus enables attainment of a bipolar transistor including a base having a good p-type impurity concentration distribution.
In the step (c), the concentration of phosphorus introduced into the semiconductor layer may be increased in stages or sequentially toward the upper portion.
The second method for fabricating a semiconductor device of the present invention includes the steps of: (a) epitaxially growing a p-type second single-crystal semiconductor layer functioning as a base layer on an n-type first single-crystal semiconductor layer functioning as a collector layer on a substrate; (b) epitaxially growing a third single-crystal semiconductor layer on the second single-crystal semiconductor layer; (c) doping at least an upper portion of the third single-crystal semiconductor layer with a p-type impurity; (d) forming a semiconductor layer containing phosphorus on the third single-crystal semiconductor layer; and (e) performing heat treatment for diffusing phosphorus in the semiconductor layer so that the upper portion of the third single-crystal semiconductor layer is doped with phosphorus in a concentration higher than the concentration of the p-type impurity introduced in the step (c), to form an emitter of a bipolar transistor.
By the above method, due to the existence of the p-type impurity introduced into the upper portion of the third single-crystal semiconductor layer in the step (c), the p-type impurity in the second single-crystal semiconductor layer is prevented from diffusing during the subsequent heat treatment, as was found out experimentally. This enables attainment of a bipolar transistor including a base having a good p-type impurity concentration distribution.
The step (c) may be performed simultaneously with the step (b) by epitaxially growing the third single-crystal semiconductor layer while being doped with the p-type impurity, or may be performed after the step (b) by implanting ions of the p-type impurity in the third single-crystal semiconductor layer.
The method may further include the steps of: forming an insulating layer on the third single-crystal semiconductor layer after the step (b) and before the step (c); and forming a semiconductor layer containing a p-type impurity on the insulating layer, wherein the step (c) is performed by introducing the p-type impurity into the third single-crystal semiconductor layer from the semiconductor layer via the insulating layer.